It can provide rates up to 250 Msps, resulting in a usable analog bandwidth of up to 200 MHz. The N320 has a higher maximum analog bandwidth than the N310.
Due to number of connectors required to provide the large number of LO outputs, the N321 does not have a front-panel GPIO connector. The N321 also has the ability to export its LO up to four times, making it possible to share LOs between a large number of N321 devices without having to provide an external, separate LO source. The N320 has a single input for the TX and RX LOs, respectively. The difference between the N320 and the N321 is in its LO sharing capability. It has two daughterboards, each has one ADC/DAC and provides one RF channel.
The N320 is a 2-channel transmitter/receiver using discrete components instead of an RFIC.
LO sharing between multiple devices (N321 only). Below 450 MHz, an additional LO and mixer stage is used to shift the signal into the range of the main LO stage. Supported master clock rates: 200 MHz, 245.76 MHz, 250 MHz. Also, it does not have connectors for external LOs. It has 2 TX/RX channels (on a single daughterboard the daughterboard itself is the same as the N310) and a smaller FPGA (XCZ035). Note that the product code "N310" refers to the module consisting of mother- and daughterboard, the daughterboard itself is referred to by its codename, "Magnesium". It has two daughterboards with one AD9371 each every daughterboard provides two RF channels. The N310 is a 4-channel transmitter/receiver based on the AD9371 transceiver IC. Tunable down to 1 MHz in UHD however performance is not guaranteed. Below 300 MHz, additional LOs and mixer stages are used to shift the signal into the frequency range of the AD9371. Supported master clock rates: 122.88 MHz, 125 MHz, 153.6 MHz. N310/N300 4-channel/2-channel Transceiver The following USRPs are variants of the N3XX series: The N3XX series of USRPs is designed as a platform. Runs MPM (see also The Module Peripheral Manager (MPM) Architecture). Full Linux system running on the ARM core. Xilinx Zynq SoC with dual-core ARM Cortex A9 (Speedgrade 2) and Kintex-7 FPGA (XC7Z100 or XC7Z035 depending on variant). External USB Connection for built-in JTAG debugger and serial console. External GPIO Connector with UHD API control. Internal GPSDO for timing, location, and 20 MHz reference clock + PPS. External White Rabbit time/frequency reference input support. External 10 MHz input & output (20 MHz and 25 MHz inputs also supported). 
Dual SFP+ Transceivers (can be used with 1 GigE, 10 GigE, and Aurora). Module and Motherboard/Daughterboard Revisions. Modifying and compiling UHD and MPM for the N3XX. Building custom filesystems and SD card images. Salt: Remote configuration management and execution. The Zynq CPU/FPGA and host operating system. N310/N300 4-channel/2-channel Transceiver.
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